Declaring Virtual Pins in Quartus

When the system design in FPGA gets bigger, then its much easier to break the jumbo block into sub-blocks and work on each of them. Upon testing (simulating) and synthesizing these sub-blocks independently, we can integrate these to get the final jumbo design block. This breaking and developing act makes the development easier and more error proof. Also, we can decrease the development time by handing over the sub-block design and verification to different individuals.

But, with the advantages, the breaking up of block into sub-blocks has few hurdles too. One of the significant hurdle is the increment in number of pins in the sub-blocks as compared to that of the final design. And we know that the number of pins supported by an FPGA is fixed.

Let us take an example :-
Suppose you have a Altera Stratix 4 device with 560 user I/O pins. Let us suppose the final design uses 540 I/O pins. And suppose you have divided the final design into sub-blocks A and B. Let us also suppose that "A" has 300 I/O pins usability and the "B" uses 600 I/O pins.

So, simulating and synthesizing the sub-block "A" may not be a hurdle. But when it comes to "B", you will face problem synthesizing the model because the number of pins is more than the pins supported by the FPGA. This is when Declaration of virtual pins come into our advantage.

Declaring the 60 or more pins in the design "B" will make sure that the design is synthesized by the Quartus tool.

Following are the steps to declare the virtual pins in Quartus:-
* We assume that the project is already opened in the Quartus tool. i.e. for Altera FPGA development.

Step 1:- Goto Assignments menu at the top of the window. Then select the Assignment Editor.
This will give you the Assignment Editor window as shown in the right hand side of
the image below.

Step 2:- Click on the "new" option as shown in the image below.

Step 3:- You will now get an editable row in the Assignment Editor. Make sure that the Category
menu at the right hand top of the editor, All is selected. Then, in the editable row,
Select Assignment Name as "Virtual Pin" and Value as "On". Now double click on the
To option of the editable row. You will then get a small icon for Node Finder as shown
in the image below. Click on it.

Step 4:- In the Node Finder window, you will see two big boxes with few options. Click on the
List option to get all the I/O pins being used in the sub-design in the left box.
Select the pins which you want to declare as virtual pins. Move this to the right hand
box. It will look something like the image below.

Step 5:- Then click on OK. The Assignment Editor will show the various virtual pins which you
declared. Once done with the checking, run the Analysis and Synthesis for the Project.
Verify the virtual pins declaration by checking the Analysis and Synthesis Report,
which will report the number of virtual pins used.


This technique of using virtual pins enables us to verify the designs of sub-blocks where the number of used pins is more than the pins available in the FPGA.

Is Skype worth $8.5 billion ?

There has been much of a debate on whether Skype is worth the amount Microsoft bought it for. Here is my side of the analysis.

Skype has a total user base of 663 millions. Of the 663 million users, only 6% are pay users. These 6% generated revenue of $860 million in the year 2010 for Skype. Skype was bought at $8.5 billions by Microsoft.

Now lets talk about another web craze, Facebook. Facebook has a global user base of 600 millions. The revenues for 2010 was reported as close to $2 billions. Of this, about $1.86 billions came from advertisement. Currently, Facebook is valuated at $50 billions.

Lets start the comparison :
1) Net worth per user :-
a) Skype :- $12
b) Facebook :- $83

2) Net worth per Revenues :-
a) Skype :- 9.8
c) Facebook :- 25





Apart from the calculations, when you talk of future growth, there too Skype has more potential than Facebook. Looking at the user growth rate of Facebook, one can see that saturation is very near. So, in the near future, the difference in user base between the two will not change much.

Also, we can see that the major chunk of Facebook revenues comes from Advertisements. On the other hand Skype is fully dependent on the user charges as of now. I expect that to change in the near future.

First, Skype can plunge into the Advertisement business. With the expertise of Microsoft, they can make a big impact. One positive thing is that they are providing free quality chatting services to millions. They would not mind listening to few seconds of advertisement provided they don't have to start paying for the chat services.

Secondly, Skype can use the voice data and analyze it to generate much better advertisement hits. The voice data will give better know-how of the person than the written messages/statuses.
This voice data can be cultivated by Microsoft to use it for improving Bing. In whole, profit for both the entities.

Thus, my view is that the $8.5 billions paid by Microsoft to buy Skype is a profitable acquisition. At least, when compared to the Facebook valuation. If you think that both the giants are over-valued, then you can start fearing of the bubble.

Using Perl to instantiate Verilog modules

The detailed procedure to use perl to instantiate verilog modules has been given in the following link:-

Use Perl to Instatiate Verilog Modules By Jeremy Webb

This post is about the few problems I faced following the exact steps as per the link and the way I resolve those issues.

After downloading the package containing the .pm file and the perl script, i.e. .pl file, I tried to run make. I have not installed GCC feature in my cygwin as per now. So, there was no way I was getting the make command to run. So this is what I did.

I copied the .pm file to one of the locations already pointed by the path. To know the path, simply run the .pl file. The file will look for the .pm file in the locations defined by the path and when not found, it will send you the error report. In the error report look for the path that is assigned against @INC.

After copying the .pm file, simply execute the .pl file
The syntax would be:-
svtools.pl -i -f < Verilog_Filename >

Reference:-
Jeremy Webb's blog

Declare wires while using generate statements in Verilog

Even though there are intelligent guidelines for Verilog code writing, people rarely follow it. One of the cases is of declaring ports (wire and reg) in the verilog code.

Two common mistakes made while declaring ports are :-
1) Not declaring wire of single bit width.
2) Declaring wire in the middle or end of the code.

Guidelines will tell you to always declare ports and that too in the initial part of the code. Making the above mistakes may cause great problems, especially when the code contains generate blocks.

When generate blocks are used, the wires which are not declared above the generate block are generated for the instantiated blocks. The important fact here is that, these wires which are locally generated are inaccessible to the other upper level modules. Even if you declare wires after the generate block ends, it will perform the same above mentioned task. So, if you are making use of these wires to design the output, you will have serious problems in the operation of the code. The wires will be always low for the upper level modules.

An example is given below.


Here, dataOutTemp of the Test module will be always low. This will make dataOut of Test module tied to zero. To avoid such problems, always declare ports before the actual design code.

In the above case, to rectify the problem, we should declare the dataOutTemp as wire in line 11.