Technology and Management

Success at the sacrifice of Principles

2012-02-13T08:12:00.000-08:00

Ever since I started the MBA, I have consistently been in a fix over the priority common people set between success and their principles. It seems, in Nepal, most of us are ready to murder our principles even for "free-lunches". So, it is quite common to find people sacrificing principles for their "success". But my question is " Is the success achieved by sacrificing principles really a success ?"

Let us take a reference. I dream of building a billion dollar company. But, if I start compromising on my principles,... on the business ethics,... on my social responsibility, then even if I achieve the dream, will I be satisfied at my "success"?

The world today seems to be filled with corruption of minds and souls. Ethics has been removed from dictionary a long time ago. And, the primary goal of people is to get rich rather than make a significant impact in the betterment of the society while earning profits.

I believe "successful" people do reflect on their actions and achievements. Even if you are envied by your colleagues and the society, what if you doubt your achievement? What if you regret that you could have got whatever you have even by holding your principles? Will your "success" really mean big to you?

My Experiences with Truth : Part 1

2011-10-20T07:44:00.001-07:00

After working for more than 3 years in India in the field of VLSI, I returned to Nepal with high hopes of starting something big. Its not that I had expected my entrepreneurial trip to be a smooth ride, but there were many aspects of the trip that I had never considered, which in fact haunted me during the ride. The journey is on hold at the moment.

My experiences with Truth is my findings and learning on this journey.

When I returned to Nepal, I had two paths to walk onto. I could either start something on the internet, like the e-commerce sites or something to do with industrial automation (using robotics) / peripheral electronics products (like printers, scanners, etc).

Both the paths had their share of goodies and baddies. Doing something on the internet meant I would be stepping into a new territory, but if you view from the investment side, it wasn't going to need a lot of investment. If you look at the electronics product manufacturing venture, it would require lots of investment and more importantly - skilled manpower. But on the flip-side, it would mean that I would be doing something that I have always loved.

And what did I choose? The easy path (at least at the beginning), i.e. building an e-commerce site.

Myself and a friend had this wonderful concept of an internet mall, giving spaces to brick-and-mortar shops and let them sell their stuff in the internet. The idea was a rocking one, because it would save the shops from the cost and unnecessary pain of developing individual website and maintaining it. We would charge a simple premium for it.

We started the project with myself looking at the technical and operational aspects and my friend looking at the marketing aspect. I took the open source e-commerce platform " opencart " and customized it to my needs. The basic site was done in 15 days. Then came the long testing and modifying phase. This was a very painful phase, because every now and then the site used to have problem, and it really sucks to solve it without proper web-site building experience. Anyways, I finished the site after a month and then the marketing started.

We had lots of issues during the marketing phase. Most of it was due to the unknown market we were targeting. The site was one of its kind in Nepal, so it was not really tested before. All we did was thought of the idea to be amazing and started to work on it. And new things are really resisted by the conventional market. Changes are always difficult.

After a month, we still had no customers. The shops who had previously shown interest had already built their own e-commerce sites. And some were just not convinced of the benefits of e-presence.

Three months into the project, our patience was running out. This is where the learning comes. When you starting a venture, you will have a very turbulent time, with lots of ups and downs. If you don't love what you are doing, then this is the time, most business commit suicide. The entrepreneurs just can't take the blow, because at one end they are not getting revenues and at the other end they are not loving what they are doing.

This is the learning of Part 1 of my journey. If you are to do something new, always do it in the field you know and you love, because there will be tides in your way, and only your love towards what you are doing will give you the courage to be patient and sail through the bad time.

Remember, always do what you love (of course it needs to be profitable on the long run).

Setting Password on PLANET ADSL Router

2011-10-13T08:01:00.000-07:00

Goto the router by typing 192.168.1.1 in the browser.

Then goto Network -> WLAN -> Security as shown in the figure below.

Then select the Select Encryption as WPA(AES) as shown by circle number 4 in the figure.

As shown in circle 5, set the desired password and save the settings.

Connecting Plastic coated Wires

2011-10-10T21:23:00.000-07:00

When connecting wires which are coated with plastic like in case of audio output wires and telephone cables, you need to get rid of the plastic coating at the ends so as to connect them in a conducting manner.

For this, take the ends and use fire or a blade to remove the plastic coating. Then only connect the wires.

This may seem a trivial thing to many but I found out that non-technical people mostly connect the wires with the plastic coating on and they burn their head trying to figure out why it didn't work.

Also, it was found that in some cases, instead of plastic, paint was used. Paint acts as insulator as well as a color coder for the wire.

Servo Motor Problem : Clean up the shaft

2011-10-10T20:33:00.000-07:00

The servo motor in my house, which is used to pump water stopped working last night. It was giving a small humming noise and was actually eating up power ( I switched on the light and the power of light went down when I switched on the motor). But, water was not being pumped. And also absent was the big sound it creates when pumping water.

First, I checked the wire connections to see if there was any discontinuity. But that was fine.

Then I opened up the back end of the motor, where the fan is situated. Refer to the highlighted screws in the image below to open up the back-end. I opened the back part, and cleaned up the shaft that holds the fan. Due to the accumulation of dust and mostly hair in the shaft, the rotor was not movable during normal operation. Only, after cleaning the shaft did the rotor work properly. After cleaning the shaft and manually rotating the shaft for few rotations, I put the back-end back to the motor.

Hurrah ! I had the motor working again.

Generating Android app for a website

2011-09-28T08:20:00.000-07:00

If you want to generate an Android app for the website you just designed, all you need to do is go to a website :- Appsgeyser

The website simply generates an Android application short-cut for your website. You will have an icon of your choice(select a proper image file) in the Android app list and this will act as your short cut to the website while browsing from Android.

I generated my Android App for the website 977 Mall.

PS :- The output App from the appsgeyser site is a APK file. You will be required to enable the settings for install from third party in the Android machine.

Light in a bottle - Recreation

2011-09-13T08:48:00.000-07:00

After watching the video on Light in a bottle by Isang Litrong Liwanag Foundation , we tried to recreate this.

Requirements :-
1) A clean transparent bottle.
2) Pure drinking water.
3) Bleaching powder.
4) Dark room environment.

Steps :-
1) Put the water and bleach powder into the bottle. Stir it well and then seal the lid.
2) Put the bottle in a dark room environment, with upper half above the environment and the lower half in the environment.
3) Expose the upper half of the bottle to the sunlight.

Results :-
1) The fluorescent light generated was awesome. Check the link

* Notes :- Need to find out the duration for which the bottle continues to glow without adding further bleach powder.

Finite State Machine Compiler and Explorer in HDL

2011-07-31T03:20:00.000-07:00

When compiling the HDL code, FSM Compiler and FSM Explorer come into picture. These tools hugely optimize the resource used by the logic in terms of space and timing.

FSM Compiler :-
-> It automatically detects state machines in the source code.
-> Implements the state encoding depending on the number of states present in the state machine, i.e.
    a) 0-4 states :- Sequential encoding.
    b) 5-24 states :- One hot encoding.
    c) >24 states :- Gray encoding.
-> Performs reachability analysis, i.e.
    a) optimize away all state that can't be reached.
    b) optimize all transition logic that can't be reached.

FSM Explorer :-
-> Uses Finite State Machines extracted by the FSM Compiler.
-> Runs through each encoding style as discussed in the FSM Compiler segment. And this tool will select the best (most performant) implementation.

Nepal Telecom ADSL settings for PLANET router

2011-07-31T03:04:00.000-07:00

The steps to follow are:-

1) Connect the computer to the router via a point to point connector.

Point to Point connector

2) Setup the wired lan connection with the router.

3) Access the router.
Do this by opening any internet browser, i.e. Goolge Chrome or Internet Explorer, or Mozilla Firefox, etc. and type in http://192.168.1.1.

4) In the Network Section, click on WAN.

5) Fill the fields with values as shown in the following pic. :
In the username and password (shown by the green ellipses) fill in the details as provided by the Nepal Telecom.

6) Click on the Save button given at the end of the page.

7) Then goto Admin section and click on commit/reboot. Click on Reboot.

The system will go for a reboot. When the router comes up, you will be able to access the internet. Yippie ! ! !

Motor control via parallel ports of a PC : A failed project

2011-07-31T02:28:00.000-07:00

It was the summer of 2007, when a friend came with a proposal. A proposal to build a control system to control the movement of an object along a fixed straight line. The object had to be moved to a certain distance from the initial location along a straight line.

I took up the project and used a simple motor control logic to build the system. The computer parallel ports were used to send the control signals to the motor. The motor and control signals were in fact isolated by the optocoupler. These are electrical isolaters, which isolate the current from computer to the ones in the motor. The main purpose of its use is to isolate the back current from the motor from reaching the computer ports. Without isolation, the computer ports would just burn away upon significant back current.

The motor then controlled the distance that would be covered by the object from its original location. A simple screw would convert the rotational movement of motor to linear movement of the object.

When I tested the whole circuit to control the objects' movement using my computer, it worked great.

But, when I took the circuit and tried to run the same code in Lab's PC, it showed a random behavior. I tried to debug it but to no avail. The motor would move the object to a random location when the computer sent the control signals.

I took the circuit back to the room and checked. It ran perfectly.

Even after several debugging sessions, I couldn't know the exact reason of the failure of the circuit.

Compiling top file in the beginning during Simulation in Verilog

2011-07-26T05:55:00.000-07:00

Generally, we tend to compile the top verilog design file at the end, i.e. after compiling all other sub-blocks. Although this is a very good practice while synthesizing the code, you may face problems during synthesis and simulation if you are using `defines in your code to instantiate modules or signals conditionally.

Follow the following example:-

If you compile the sub block first and then compile the top block, then the output would be an OR gate. That is because, when the sub-block is being compiled, ANDGATE is not defined as yet. So, the OR gate would be instantiated.

But, if you compile the top file and then compile the sub-block, then AND gate would be instantiated, as the sub-block detects the ANDGATE to have been defined earlier.

So, it is a good practice during simulation, to compile the top block before the sub-blocks.

Do not use % in the verilog code during Verilog Synthesis

2011-07-22T06:27:00.000-07:00

When you need to find the remainder of a division operation, then %, i.e. Mod, is used. Suppose you want to find the remainder when 4 is divided by 3 then the code to implement is :-

When you are designing complex logics, use of Mod or % makes your work easier and also the code is more readable. The simulation of code with use of % works fine. But, when you move to synthesis, the code takes up so much time to synthesize. And honestly, I don't know if it will ever synthesize. I had a piece of code with % used at multiple places. After waiting for 40 odd minutes, the synthesis just stuck at 80%. It was trying to synthesize but I couldn't wait longer. After removing the % from the code, I got the whole code synthesized in less than 10 minutes. :)

So my advice to all the verilog coders will be to Feel free to use % if the code is meant for simulation. But Avoid usage of % in code that is to be synthesized. Rather use if..else statement, however lengthy they may be.

Verilog Simulation : Sensitivity list for a combinational logic

2011-07-22T06:15:00.000-07:00

An interesting find today while I was simulating a big chunk of code. The problem occurred in the combinational always block. By rule, we have to put all the inputs to the combinational block in the sensitivity list.
Eg for a simple and gate with input inpA and inpB and output as outAndAB, the coding goes as:-

And if you simulate this design, the code will work fine. But when you move to complex combinational block designs, it is easier and better to assign * in the sensitivity list. In my design I had similar code implemented in three places. While the two worked fine, I got issues in the third implementation. The output didn't get modified when the input changed even though the inputs were there in the sensitivity list. I tried putting the *, which means all, in the sensitivity list and it worked. The tool will optimize the * and put all required signals in the sensitivity list when simulating the code.

After the change the code for the And gate will be :-

So, remember to always put * in the sensitivity list of a combinational block.

Default values of Reg and Wire in Modelsim Simulation

2011-07-18T07:42:00.000-07:00

Ever wondered what is the default value assigned to a reg or a wire during simulation?
Well, a reg has a default value of HiZ (High Impedance) while a wire has a default value of X (Don't Care) in Modelsim simulation.

Verification :-
a) Input Module :

b) Output Waveform :

*Note:- Simulation results of Modelsim SE 10.0

Run TCL file in Modelsim

2011-07-18T06:25:00.000-07:00

Testing of logic designs in Modelsim can be automated using TCL files. To run TCL file in Modelsim, follow the two simple steps :-
Step 1 :- Write the TCL file.

Step 2 :- Open Modelsim. Goto Tools -> Tcl -> Execute Macro. And then select the tcl file.

Computer Systems : Internal hard disk drive not found

2011-07-17T00:22:00.000-07:00

I got this error while booting up my Dell Latitude. The screen said that the system could not find the internal hard disk drive. I was in shock. I tried googling up the issue but to no avail. I even jacked out the system RAMs and cleaned its connectors. I also removed the battery and put it back after few minutes.

After these failed approaches, I entered the BIOS setup to see if the BIOS is actually reading the hard disk or not. If BIOS can't read it then its time to buy new hard disk. With lots of combinations and permutations, I finally hit the nail's head.

I solved the problem in two simple steps:-
Goto the BIOS setup page. This page may look different based on the Dell laptop model.
Step 1 :-
In the Boot Sequence, which is inside the General Settings, move the Internal HDD to the top. This will ensure that the system will first look up into the internal HDD for boot programs. By default, the floppy disk(diskette) drive is set to highest priority.

Although this is not a major problem, but setting internal hdd as highest priority will not have any side effects, as the laptops these days lack the floppy disk drives, which are set to the highest priority in default conditions.

Step 2:-
Next goto the SATA Operation settings, which could be in System Configuration or the Device Info depending upon the laptop model. Set this to ATA.

Why does this problem occur?
Due to improper shutdowns or deletion of files in the windows folder, the BIOS settings would have modified. As the SATA operation setting, that defines the operation of hard disk, is set to some other than ATA, the system can't read the hard disk.

Notes:-
1)This problem was faced in Windows XP and thus could/couldn't work on other Operating systems.
2)The solution worked on Dell Latitude and Inspiron laptops. For other models, you need to verify.

Bash : syntax error in expression (error token is "12")

2011-07-15T20:38:00.000-07:00

If you want to read a file line by line then you can follow the post in the link
When you echo this line to the display or to another file, then there seems to be no issues. But, when you try to store the line contents to a variable,
Eg:-
temp=$line
then you could get the error :-
syntax error in expression (error token is ".....")

This error occurs if the file, from which we are reading the lines, contains carriage return-line feed . The solution to this problem would be to strip the carriage return-line feed from the $line when it is being assigned to temp variable.
Solution :-
temp=${line//$'\r'}

Remember, if you want to assign temp again to another variable, then too you have to follow the same syntax of assignment as given in the solution.

Reading a file word by word in bash

2011-07-15T06:47:00.000-07:00

Reading a file word by word in bash can be done in the following two steps :-
Step 1:- Read the file one line at a time and buffer it

Step 2:- Read the buffered line one word at a time

So, combining the two, we can read a file word by word. The final code is :-

Verilog :- Why not to use Blocking Statements in Sequential Logic Design

2011-07-03T02:16:00.000-07:00

Although there is no golden rule in verilog as to which type of statements to use while designing sequential circuits, it is highly recommended that non-blocking statement be used while designing such circuits.

It is a very good and almost an essential practice to use blocking statements to design combinational block and non-blocking statements to design sequential logic.

When you have multi-cycle paths to be designed as a sequential logic, then the use of blocking statements usually leads to optimisation/trimming of the logic. For a 2 cycle delay, you will only get a single cycle of delay. Consider the following example :-

Case 1:- Sequential logic design with non-blocking statements:

Code:-

Rtl Schematic :-

Case 2:- Sequential logic design with Blocking statements:

Code:-

Rtl Schematic :-

So, non-blocking statements should be used while designing Sequential blocks in Verilog.

*Note :- The synthesis of code and rtl schematic generation were done using Xilinx ISE Release Version : 9.2.04i

Declaring 2D Array I/O Ports in Verilog

2011-06-22T09:06:00.001-07:00

2D arrays in verilog can be declared as :-
wire/reg [column_limit : 0] [0 : row_limit] ;

Eg:-
wire [7:0] byteMem [0:31]; => this creates a wire array of 8 bits * 32.

Using 2D arrays in verilog is a very tricky thing. System verilog supports 2D arrays but verilog seems to treat it as an estranged friend. Flexibility in assigning and accessing the 2D arrays are very hard. But as always, there are work arounds.

Verilog doesn't support 2D arrays as I/O ports. But there are cases when using and accessing 2D arrays are more efficient in reducing the code lines as well as improves the readability of the code. The work around for this is to declare the I/O ports as 1D array and use 2D wire internally which is then assigned the value as in the I/Os.

Suppose you need an output of 8bytes * 4 locations.
1) Assign the output as array of (8*4) width, i.e. [8*4-1:0]
2) Use an internal wire/reg array of 8bytes * 4 locations :-
wire [7:0] temp [0:3];
3) Using generate statement, assign the temp 2D array to store the values of the output array.
*Note :- A simple define could be used to assign the values. Refer to Comment #7 on the link below for more. Comment #7.

Simply use the macros defined in the link to implement virtual 2D array output/input ports.

Cygwin : "bash: $'\r': command not found"

2011-06-13T09:47:00.000-07:00

When we copy bash scripts, edit them and then try to run these on the Cygwin, many a times we get the error :-
"bash: $'\r': command not found".

I don't know the exact reason for this, but it seems the bash can't read the file properly, so we need to use the dos2unix.exe command in the cygwin to convert the script to readable format. This solves the problem.

Syntax :- dos2unix.exe scriptname .

Then run the script. It should run fine.

Declaring Ports in Verilog

2011-06-12T09:05:00.000-07:00

Declaring ports in Verilog can be a tricky issue for beginners. Here is a brief of how and what to declare a port in Verilog HDL.

We will start dividing the ports on the basis of their location, i.e. input/output and on the basis of their behavior, i.e. registered data or simple wires.

On the basis of Location:-
We can group the ports into three on the basis of their locations :-
1) Input ports,
2) Output ports, and
3) Inout ports.

The input ports are basically the pins from where the data and signals reach the block. The output ports are the pins from where the data and signals leave the block. And the inouts are ports which can act as input and output during the run time.

On the basis of Behavior:-
We can group the ports into two on the basis of their behavior:-
1) Reg
2) Wire

If you want the data to be registered, then declare the port as reg. This will store the data/signal, which can be used later in the design. On the other hand, if you just want a signal to propagate from one point to another without any delay or storage, then declare it as the wire.

Even the inputs/outputs/inouts need to be declared on the basis of their behavior. Inputs are always wires, inouts are also always wire but outputs can be declared as wires or regs based on their behavior.

Refer to following diagram :-

Diagram Reference :- www.asic-world.com

Declaring Virtual Pins in Quartus

2011-05-27T20:30:00.000-07:00

When the system design in FPGA gets bigger, then its much easier to break the jumbo block into sub-blocks and work on each of them. Upon testing (simulating) and synthesizing these sub-blocks independently, we can integrate these to get the final jumbo design block. This breaking and developing act makes the development easier and more error proof. Also, we can decrease the development time by handing over the sub-block design and verification to different individuals.

But, with the advantages, the breaking up of block into sub-blocks has few hurdles too. One of the significant hurdle is the increment in number of pins in the sub-blocks as compared to that of the final design. And we know that the number of pins supported by an FPGA is fixed.

Let us take an example :-
Suppose you have a Altera Stratix 4 device with 560 user I/O pins. Let us suppose the final design uses 540 I/O pins. And suppose you have divided the final design into sub-blocks A and B. Let us also suppose that "A" has 300 I/O pins usability and the "B" uses 600 I/O pins.

So, simulating and synthesizing the sub-block "A" may not be a hurdle. But when it comes to "B", you will face problem synthesizing the model because the number of pins is more than the pins supported by the FPGA. This is when Declaration of virtual pins come into our advantage.

Declaring the 60 or more pins in the design "B" will make sure that the design is synthesized by the Quartus tool.

Following are the steps to declare the virtual pins in Quartus:-
* We assume that the project is already opened in the Quartus tool. i.e. for Altera FPGA development.

Step 1:- Goto Assignments menu at the top of the window. Then select the Assignment Editor.
This will give you the Assignment Editor window as shown in the right hand side of
the image below.

Step 2:- Click on the "new" option as shown in the image below.

Step 3:- You will now get an editable row in the Assignment Editor. Make sure that the Category
menu at the right hand top of the editor, All is selected. Then, in the editable row,
Select Assignment Name as "Virtual Pin" and Value as "On". Now double click on the
To option of the editable row. You will then get a small icon for Node Finder as shown
in the image below. Click on it.

Step 4:- In the Node Finder window, you will see two big boxes with few options. Click on the
List option to get all the I/O pins being used in the sub-design in the left box.
Select the pins which you want to declare as virtual pins. Move this to the right hand
box. It will look something like the image below.

Step 5:- Then click on OK. The Assignment Editor will show the various virtual pins which you
declared. Once done with the checking, run the Analysis and Synthesis for the Project.
Verify the virtual pins declaration by checking the Analysis and Synthesis Report,
which will report the number of virtual pins used.

This technique of using virtual pins enables us to verify the designs of sub-blocks where the number of used pins is more than the pins available in the FPGA.

Is Skype worth $8.5 billion ?

2011-05-21T00:51:00.000-07:00

There has been much of a debate on whether Skype is worth the amount Microsoft bought it for. Here is my side of the analysis.

Skype has a total user base of 663 millions. Of the 663 million users, only 6% are pay users. These 6% generated revenue of $860 million in the year 2010 for Skype. Skype was bought at $8.5 billions by Microsoft.

Now lets talk about another web craze, Facebook. Facebook has a global user base of 600 millions. The revenues for 2010 was reported as close to $2 billions. Of this, about $1.86 billions came from advertisement. Currently, Facebook is valuated at $50 billions.

Lets start the comparison :
1) Net worth per user :-
a) Skype :- $12
b) Facebook :- $83

2) Net worth per Revenues :-
a) Skype :- 9.8
c) Facebook :- 25

Apart from the calculations, when you talk of future growth, there too Skype has more potential than Facebook. Looking at the user growth rate of Facebook, one can see that saturation is very near. So, in the near future, the difference in user base between the two will not change much.

Also, we can see that the major chunk of Facebook revenues comes from Advertisements. On the other hand Skype is fully dependent on the user charges as of now. I expect that to change in the near future.

First, Skype can plunge into the Advertisement business. With the expertise of Microsoft, they can make a big impact. One positive thing is that they are providing free quality chatting services to millions. They would not mind listening to few seconds of advertisement provided they don't have to start paying for the chat services.

Secondly, Skype can use the voice data and analyze it to generate much better advertisement hits. The voice data will give better know-how of the person than the written messages/statuses.
This voice data can be cultivated by Microsoft to use it for improving Bing. In whole, profit for both the entities.

Thus, my view is that the $8.5 billions paid by Microsoft to buy Skype is a profitable acquisition. At least, when compared to the Facebook valuation. If you think that both the giants are over-valued, then you can start fearing of the bubble.

Using Perl to instantiate Verilog modules

2011-05-07T05:22:00.000-07:00

The detailed procedure to use perl to instantiate verilog modules has been given in the following link:-

Use Perl to Instatiate Verilog Modules By Jeremy Webb

This post is about the few problems I faced following the exact steps as per the link and the way I resolve those issues.

After downloading the package containing the .pm file and the perl script, i.e. .pl file, I tried to run make. I have not installed GCC feature in my cygwin as per now. So, there was no way I was getting the make command to run. So this is what I did.

I copied the .pm file to one of the locations already pointed by the path. To know the path, simply run the .pl file. The file will look for the .pm file in the locations defined by the path and when not found, it will send you the error report. In the error report look for the path that is assigned against @INC.

After copying the .pm file, simply execute the .pl file
The syntax would be:-
svtools.pl -i -f < Verilog_Filename >

Reference:-
Jeremy Webb's blog

Declare wires while using generate statements in Verilog

2011-05-04T05:05:00.000-07:00

Even though there are intelligent guidelines for Verilog code writing, people rarely follow it. One of the cases is of declaring ports (wire and reg) in the verilog code.

Two common mistakes made while declaring ports are :-
1) Not declaring wire of single bit width.
2) Declaring wire in the middle or end of the code.

Guidelines will tell you to always declare ports and that too in the initial part of the code. Making the above mistakes may cause great problems, especially when the code contains generate blocks.

When generate blocks are used, the wires which are not declared above the generate block are generated for the instantiated blocks. The important fact here is that, these wires which are locally generated are inaccessible to the other upper level modules. Even if you declare wires after the generate block ends, it will perform the same above mentioned task. So, if you are making use of these wires to design the output, you will have serious problems in the operation of the code. The wires will be always low for the upper level modules.

An example is given below.

Here, dataOutTemp of the Test module will be always low. This will make dataOut of Test module tied to zero. To avoid such problems, always declare ports before the actual design code.

In the above case, to rectify the problem, we should declare the dataOutTemp as wire in line 11.

Async FIFO Depth Calculation

2010-12-21T02:39:00.000-08:00

When data transfer is to be done between different clock frequency domains, Async FIFOs are used. These FIFOs provide a medium to avoid data loss due to difference in the two frequencies.

The calculation of Async FIFO Depth is the most important part in designing the inter-clock domain data transfer system. The FIFO Depth is dependent on the number of data bits to be transferred in one cycle and the difference in the frequencies of the clocks.

CALCULATION :-

Let the incoming data to the FIFO be at F1 Frequency, i.e. write frequency.

Let the reading be done at F2 Frequency.

Suppose, B number of bits are being written and read per cycle, then

FIFO Depth = B - (B/F2)*F1 , if F2 > F1
else
FIFO Depth = B - (B/F1)*F2 , if F1 > F2

Factors Determining the Demand of Product

2010-12-16T03:55:00.000-08:00

The period in which a product is perceived, designed, developed, tested and sold is known as product cycle. Modifications in the product may be demanded by the customers, thereby triggering the second rotation of product cycle.

When a new product comes to the market, the demand of the product is directly proportional to the functionality offered by the product. At first, this is the only product providing the required functionality by the market, thus can be sold at high premium. This attracts other vendors too to design such products. Similar functionality offering products enter the market. This is when the products can not ask for high premiums, as the market is saturated in terms of functionality offered by the product.

The customers want reliability of product to be the criteria for paying premium on the products. The product offering better reliability like shake free, water resistant, temperature independent, etc will have higher profit margins. This will again lead to overcrowding of such products from various vendors in the market.

After functionality and reliability have reached the market demand levels, the searching parameter changes to convenience. Demand is driven by the level of convenience the product can provide like ease of use/handling, moving the product.

Finally, when all other criteria are met by almost all the products, the price of the product plays the most important role in determining the demand of the product.

What sort of companies do venture capatilists like?

2010-05-09T00:59:00.000-07:00

As follows:-

1) Promoters having large static as well as dynamic stakes in the company.
2) Promoters fully dedicated to the company. Part time working promoters are a no no.
3) Promoters with impressive history and/or strong work ethics.
4) A promise of long term benefits.
5) Strong and intelligent work force.
6) Mature management group.
7) Clarity of the financial reports.

The use of "WHY" by business leaders

2010-05-09T00:43:00.000-07:00

What separates the business leaders from the normal people who "practice" business, is that the leaders always ask the question "why" when they are taking decisions. While the normal people are happy just to follow what top CEOs or top management gurus tell them or what the traditional reaction theory indicates, the leaders ask the all sort of questions like why should we follow the tradition,is it loss-proof? Why the management gurus are to be listened, are they right?

These sort of questions make sure that when the majority of people face dire losses when the gurus and the tradition fails, the leaders smile with a bucket of profit. Always do your calculations and analysis. Never take decisions solely because some top business person has taken similar decision. Never take decisions just because those proved correct in the past. Analyze and then take decisions. Always ask "why".

Cooking vegetables and Entrepreneurship

2010-03-01T03:10:00.000-08:00

Caution :
Well I am no entrepreneur..neither am i a professor ..nor a guru teaching people about entrepreneurship. This post is solely based on the observation I have made and I don not guarantee any proof of whatsoever kind that the conclusion I made from my observation is cent percent true.

Entrepreneurship has always been an interesting subject to me. Reading about global entrepreneurs has been a hobby kinda thing for me. Last Saturday, I was in my kitchen trying hard to cook some vegetables. This is when I found out that there are numerous teachings a man/woman/other can get about entrepreneurship while cooking vegetables (Could be non-vegetable items too. But being a supporter of PETA, solely because of the bullet girls that campaign for them, I would only use the reference of vegetables).

First, begin with the shopping of right vegetables and spices. This is similar to searching the right resources for your company. The resources mean human as well as non-human resources. The better you get, the better your end product will be. Also, the price factor is to be kept in mind. The better the product you make, the better your profit is going to be.

Next lesson you learn is when you start chopping vegetables. Once in a while you may get cuts and bruises. This is similar to an entrepreneur experiencing down periods in his financial performance. These bruises shouldn't take your enthusiasm away. These bruises and cuts will teach you to be more alert in the future. Also, as you gain experience, these events of cuts and bruising will minimize.

Now, when you have cut the vegetables and kept the pan on the heater, you have to take major decisions. Whether the food is going to be totally fried, or totally boiled or a mixture of it. Similar to this, an entrepreneur must have a focused plan for his company. Whether his company will be an IT product/service company or a non IT one. And among these also, he has to choose the various options to be sure of the kind of final product he wants to make.

In the middle of the cooking, you have to add spices. The perfect amount of salt. The perfect amount of ginger paste, chilly, turmeric, etc. An entrepreneur too must hire right number of people for management purpose, R&D purpose, maintenence purpose, etc. Also, a similar choice is to made while dividing the budget for each of these departments. Extra salt would ruin the taste of the food.

The ideal time for cooking vegetables is a very interesting value. It depends on a number of variables like the method of cooking, the type of pan used for cooking, the vegetables used, the taste preferred by the consumer. In industry too, the time taken to make the products are constrained by various variables. The complexity of the product. The efficiency of the R&D, production and sales team. The time when the demand in the consumer market would be maximum.

And, finally when the vegetable is cooked, the way you serve it can make a big difference. An entrepreneur has to read the mind of the consumers and present the products accordingly. Advertisements, gala-openings, discounts, etc come into picture. Selling is an art. So is decorating the food while serving it.

I think it would thus be safe to say that cooking vegetables is a crash course to an individual dreaming of being an entrepreneur.

FPGA : Sacrificing resource sharing for better timing

2010-02-19T09:18:00.000-08:00

When it comes to any system design, the most important part is the optimum utilization of the available resources. Talking of system design with FPGAs, the resources mean the PLLs(Phase Locked Loop), RIOs(Rocket IOs), DCMs(Digital Clock Manager), BUFGs(Global Buffers), FFs(Flip-Flops), LUTs(Look Up Tables) and dedicated block rams.

There are numerous vendors supplying FPGAs in the market like Xilinx, Altera, Lattice, etc. All these vendors supply a wide range of FPGAs. Suitable FPGA should be selected depending upon the system resources required for your design and the resources available in the FPGA.

After the synthesisable code describing the system has been written, generating FPGA build takes two major steps. First, the code must fit the device selected and secondly, the design must meet the timing constraints (set up time, hold time, period constraints).

Most of the tools used to make FPGA builds available these days try to optimise the code and try to fit it in the device taking as less resources as it can. One of the logic used for optimising code is Resource Sharing.

Resource sharing is a technique where multiple logic blocks of the designed system share a common logic block. Let us take an example of a system which can add and subtract two input bits. The system can be thus divided into two major blocks of Addition of these two bits would give a bit each of Sum and Carry. Meanwhile, a subtractor would have a bit each of Difference and Borrow as its outputs. As we write the truth table we see that the sum and difference outputs have same logic design. If we try to make FPGA build with the code describing the above mentioned logic, the tool will infer only one logic block for generation of output difference and sum, i.e A XOR B (where A and B are input bits). And the tool will also try to place this block in the FPGA which will be equidistant from the outputs sum and difference.

This sharing of A XOR B block by the adder and subtractor block is known as resource sharing. This leads to optimum resource(FFs and LUTs) utilisation.

Referring to the above figure, we can see that if two logic blocks of A XOR B were generated, one each for sum and difference, the tool would have tried to place these two blocks as following:

When we are designing the system for lower speed(lower clock), then resource sharing is the best way to go. But, when we are working at higher speed where the timing is of utmost importance while placing the blocks in the FPGA, we have to take decisions of whether to use resource sharing or not. If the timing constraints for all the clocks used are met and the system is fitting in the device, then all is well. If the fitting issues arise, then we may have to enable resource sharing(by default the tools enable this feature). If we have design fitting handsomely but with problems meeting the timing constraints, then we may have to disable the resource sharing option. This would mean using up more resources but we would be rewarded with better timings. See the design for adder plus subtractor system in figures 1.1 with resource sharing and 1.2 without resource sharing. Obviously, the figure 1.1 uses lesser resources. But, when we calculate the total path delay from A and B to outputs Sum and Difference in the two designs, we will have to conclude that without resource sharing, we are achieving better timing in terms of path delays.

Now, consider the adder plus subtractor design to be a part of a bigger design, where the inputs A and B are outputs of Flip-Flops and the outputs Sum and Difference are inputs to different Flip-Flops. Using the design represented in figure 1.2 would lead to better margins in terms of setup times and the maximum clock speed that can be used in the design.

This way, sacrificing resource sharing can lead to better timing achievements.

Inefficient cooling system design in Inspiron 1525

2010-02-14T00:28:00.000-08:00

For a couple of months, I had a problem with my Inspiron 1525 shutting down in the middle of nowhere. For some time it wasn't a very serious problem, so I just let it do all its mischief. Then, a week ago I started playing Counter-Strike. The problem repeated like anything. After every ten minutes or so, the laptop shut down. Then I thought, enough is enough I have got to find out a solution.

Ten minutes of googling led me to find a solution, thanks to Andreas .The problem was due to inefficient cooling system design in the Inspiron 1525.

The cooling system consists of a heat transfer system, which transfers heat from the processor to the sink, fan and heat sink. The sink then radiates the heat out of the laptop. The affect of radiator(heat sink) is enhanced by the fan which helps to keep the heat sink cooler. If the fan doesn't work or the heat sink can't get the effect of fan, then the sink can't radiate the heat efficiently, and thus the temperature of CPU rises causing the computer to shut down.

The problem with my laptop was that there was dirt in between the heat sink and the fan. This meant the heat sink couldn't get the proper air-flow to cool it. The result, the heat sink wasn't functioning up to its optimum level and thus the processor was getting heated. This led to my computer getting shut down repeatedly.

The solution was to remove the dirt that lied in between the fan and the heat sink.

This is something I have to do every 2-3 months. But, this could have been avoided if the cooling system had been designed in a much better way. In the above paragraph, I have described about the parts of a cooling system. There is one thing missing. And that is a filter. Basically, when the fan is operating, it takes in air from some place (some vents) and then blows the air towards the heat sink. As the name suggests, the filter filters the air coming to the fan through these vents. The result is that the air flowing from the fan to heat sink is dirt free. Thus, there is no way dust can accumulate in between the fan and heat sink.

The filter system in the laptop seems to be absent which led to occurrence of this problem. I don't know if they didn't add filter to the cooling system design for some advanced reasons or they just forgot.

Ideal time to buy shares

2009-02-11T06:43:00.000-08:00

With recession hitting almost all the countries directly or indirectly, people and corporations have started to save money and cut their expenditures. This leads to reduction in flow of money in the market. This severely damages the economy of the country. Money flow is very important for a growing economy. But, the fear of uncertain future has lead people to spend less and save more. People have liquidated a large amount of their investments. This has lead to massive devaluation of share prices of almost all the companies. For any cunning investor this is a heavenly time to invest in those shares. The market is bound to bounce back. The share prices are bound to shoot up.

The major principles laid down by Benjamin Graham, one of the teachers of Warren Buffet, are:
1) Buy shares of those companies whose share value is 2/3rd of the intrinsic value.
2) With low P/E ratio.
Intrinsic value is an element to measure the true value of one share. A simple calculation of evaluating it would be getting the net assests of the company divided by total shares.
P/E ratio is total price of one share divided by the earnings the share gives in one year. Lower P/E ratio means you will earn amount equal to share value in shortest time.
Thus analysing the current situation where the share prices have fallen to very low values, well below the 2/3rd margin and choosing lower P/E offering companies, it is an ideal time to buy shares. When the market rises out of recession, even capital gain will be in huge positive magnitude.

Also, note the pointing of Warren Buffet, who believes in buying devaluated shares of big and strong companies as these companies' shares are bound to bounce back.

Pipelining and Retiming in High Speed Digital Logic Designs

2009-02-01T23:09:00.000-08:00

Consider figure 1.1, which pretty much describes the basic block of any digital logic design. The maximum allowable frequency that can be used in a circuit design is given by the equation
Fmax=1/Tmin -------(i)
where Tmin is calculated as
Tmin=Tc-q + Tcomb + Tsu-------(ii)

Note: There may be many such circuits as figure 1.1 in complex system design with variable Tcombs. In such cases, the highest Tcomb is used to determine Tmin and the path associated with it is called critical path.

Tc-q::The time taken by the input at the flip-flop, D ,to give output Q after the trigger edge of the clock.

Tcomb::Total delay of combinational logic in between the flip-flops.

Tsu::The minimum time interval for which the input of the flip-flop must remain stable before the trigger edge of the clock.

Let us take an example:
Suppose, Tc-q=5ns, Tcomb=15ns, Tsu=5 ns
then, Tmin=25ns and thus Fmax=40 Mhz.

In digital systems, processing is basically done by the combinational logic while the flip-flops help to control the data and the processing. As technology advances, processing becomes much more complex. But as the processing becomes more and more complex, the maximum allowable frequency decreases accordingly. Thus realizing high speed Digital system design with large combinational blocks using the basic block as in figure 1.1 is not possible. This is when we need to rearrange the circuit so that high frequency can still be used.Two major techniques are widely followed in high speed digital logic design::
(i) Pipelining
(ii) Retiming

Pipelining::
Pipelining is a process by which a normal large combinational logic block between two flip-flops is broken down into two or more pieces. Then, flip-flops are inserted to isolate those pieces. When applied for critical paths, Tmin decreases, thus allowing us to use higher operational frequencies. If we try to pipeline the circuit described by figure 1.1, we would get a result as described by figure 1.2.

Suppose , Tcomb(2)=6ns
and Tcomb(3)=9ns

From the figure,
The critical path (highest path delay) in the circuit is the path from 2nd D f/f to 3rd D f/f. Thus,

Tmin= Tc-q + Tcomb(3) + Tsu
=19ns
This gives, Fmax= 52.6 Mhz.
This way, efficient pipelining can be used to increase the maximum permissible frequency for a digital design.

Retiming::
Retiming is a much complex technique, which is generally done by the help of software. Consider a circuit where the delay of combinational blocks vary greatly. Then, inspite of the fact that there are paths with low delays, we would have to consider the maximum Tcomb (i.e. of critical path) in order to obtain Tmin. This will give us comparatively low maximum allowable frequency. An example is given in Figure 1.3.

Suppose, Tcomb(4)=3ns
and Tcomb(5)=12ns

Then, Tmin=Tc-q + Tcomb(5) + Tsu
=22ns
This gives, Fmax=45.4 Mhz.

We can redistribute the combinational logic blocks in such a way that the variance in their delays is minimized. If we do this for the circuit described by Figure 1.3 we can, at the best, get two blocks of 7.5 ns.
Then, Fmax would be 57.1 Mhz.

Note: The example denotes an ideal case. In general, after rearranging, Tcomb(4) will be > =3ns and Tcomb(5) will be < =12ns.

Even if we don't get this optimal result, any decrement in the critical path delay due to this process of redistribution will enable us to use higher frequencies.This procedure is termed as Retiming.

Although the final hardware may increase due these procedures, we gain a lot in terms of maximum allowable frequency. And in case of high speed digital logic designs, the latter is given priority.

Graphene to replace Silicon in IC fabrication

2009-01-31T22:46:00.000-08:00

Silicon has been long used as the base to fabricate Integrated Circuits(ICs). But with the fabrication industry strictly following the Moore's law that packing density of chips doubles every 18 months, it won't be long before Silicon technology saturates. The signs have been seen and thus the fabrication industry is keenly searching an alternative as in near future we won't be able to increase the packing density of circuits based on silicon as it achieves saturation. One of the solution could be to use Graphene instead.

Graphene is a one-atom-thick planar sheet of sp²-bonded carbon atoms that are densely packed in a honeycomb crystal lattice. The requirement of any material to be used as substrate in IC fabrication is to have metallic, semiconductor and insulating properties either in free state and/or in compound state of that very material. The semiconductor nature helps in controlling the action of transistors(the building blocks of chips). The metallic property is needed to have high speed movement of carriers. The insulator quality is needed to isolate the transistors and also differentiate the on and off state resistance of transistors that need to have high variance.

The graphene sheet, rolled so as to form tubes, can act as metallic or semiconducting in nature based on the angle of rolling. The metallic nature of these tubes has long been appreciated by the fabrication industry. They have remarkably high electron mobilty at room temperature, with reported values in excess of 15,000 cm²V⁻¹s⁻¹. Also the mobility of holes and electrons are almost equal. The conductivity remains constant for a high range of temperatures. The semiconducting nature of graphene can be exploited by rolling the sheet at certain angle or by bending the tubes to an angle. This bending of graphene tubes decreases the conductivity at the bends and thus can be made to act as semicontuctor after some calculations. The only problem scientists were facing with graphene as a substitute of silicon was the insulating property of graphene which was very poor.

But , scientists in Manchester University have shown that graphene can be easily modified to act as an insulator by adding hydrogen atoms to its surface. The new material , called graphane, is made by exposing a graphene sheet to ionized hydrogen gas for some two hours. Until now, graphene was used to make transistors with other materials. But this process can't be used in IC fabrication due to the time and cost that comes with such processes. Commercially, this would fail. The need is of one material to be used as the base of the IC which can be then modified to act as conductor, semiconductor or insulator. Now, with this major successful experiment, graphene can be used as a subsitute of silicon. Also, this technology being new, would last for long time in the fabrication industry before it achieves its saturation. That means, it would be 10-20 years at least before we would start hunting for new material to substitute graphene for IC fabrication.

Thus, I see graphene substituting silicon in the ICs in the near future so as to fulfil the rising demand of higher speed of the market and to follow the Moore's law of doubling of packing density every 18 months.

Time for Change

2009-01-26T02:56:00.000-08:00

Change, we can.....

-U.S. President Barack Obama

"Change" is a word feared by many. People prefer routines. We are very reluctant when it comes to changing our habits.

Talking about changes, the market scenario has changed drastically over few months. The government approach on the free market has changed. The trading systems have changed over time. We have moved from barter system to gold to money and now to virtual money(debit, credit, bonds, shares, etc.) . Sea levels have risen. Ozone layer has dropped. Population has increased over past centuries. The whole atmosphere has changed. Government have changed. Everything is changing. Change is infact inevitable.

The defination of power has changed from swords, guns and missiles to knowledge. The priority of all the nations has changed from military to economy. Pen has become mightier than the sword. And to this change in time and the environment, people have unwillingly changed themselves accordingly. Even the animals and plants have adapted. But, to this day, of there is one thing/species that hasn't changed that is we .."Nepalese". We are still stubborn to accept that we fear "change" the most. Maybe its because of the legacy our Gurkha ancestors have for bravery, we can't face the fact that we fear something i.e. change.

Days are gone when courage in battlefield meant everything. Days are gone when war used to be won with guns, cannons, missiles and khukuris. Now the war is won with economics and the market is the battleground. People in almost all parts of the world have accepted these facts and moved from learning sword-swinging to accounting and finances. And , talk about us. We stand tall and refuse to change ...refuse to accpet these changes. We still feel that we are born fighters. We still feel its in our blood and we still believe sword is mightier than the pen. Look at Japan and Germany. The people there were fighters too. But now, their pen speaks, their knowledge wins the war, and for the guns and swords..those rust in museums. People in the developed nations solve problems with dialouges, meeting , conversations.

We , in Nepal, still choose violence to solve every problem. All the decisions are made by the mob and laws passed on the streets. Be it some actor from neighbouring country saying that he doesn't like our country(no one verified this...totally based on rumours..), or some movie telling Lord Buddha was born in some other country, we have always gone to the streets for solutions and burnt our mother Nepal to pacify ourself. May be to "demonstrate" that we have won....Won what?..i don't know..

Well may be to show that we are the decendants of the fierce Gurkhas. Maybe to show the world that we are still brave..errrr.. may be we are still fools as pointed out by our Maha Kabi Laxmi Prasad Devkota. We show pride in burning shops and devastating the economy. Convesations and dialouges are always lower priorities while solving issues. Violence is the defacto choice.

Maybe we are too immature when it comes to dealing with situations. Or, maybe we still believe that sword is mightier than pen. Maybe Khukuri still rules for us. It is not that we lack brilliant brains in Nepal(Nepalese have shown their brain-power in almost all fields in the world), it is because we are afraid of change. ....change in our approach to solve problems ...change the way we live....change the way we show our courage..

When the whole world is talking about change(remember ....Change, we can.....), we still fear it. Fears of having no strikes....fears of having no bandhs...fears of being governed by proper administrators...fear of not having the mob rule which we enjoy ....fear of not being able to decide things on the streets.

Well, dinasaurs didn't accept the idea of change..the idea of adaptation, so they are extinct now. The cockroaches adapted to the environmental change, so they still have their decendants living. We have to realise this fact and understand that Khukuris can't win the war for us. We must be proud of our past and also realise that we have to change our present if we are to be in the future. We have to start giving importance to knowledge. We have to start using our thick heads rather than use tyres and bricks. We have to use tourches to light the houses ...not to burn them. We need to change so as to build our economy rather than doom it. We need to accept and acknowledge the power of knowledge. We need to adapt to the changing time. We need to change. Only then, we will have a future or else just like the damn stubborn dinasaurs, we will be extinct too.

Change, we must....
-Unknown