Compiling top file in the beginning during Simulation in Verilog

Generally, we tend to compile the top verilog design file at the end, i.e. after compiling all other sub-blocks. Although this is a very good practice while synthesizing the code, you may face problems during synthesis and simulation if you are using `defines in your code to instantiate modules or signals conditionally.

Follow the following example:-

If you compile the sub block first and then compile the top block, then the output would be an OR gate. That is because, when the sub-block is being compiled, ANDGATE is not defined as yet. So, the OR gate would be instantiated.

But, if you compile the top file and then compile the sub-block, then AND gate would be instantiated, as the sub-block detects the ANDGATE to have been defined earlier.

So, it is a good practice during simulation, to compile the top block before the sub-blocks.