Declaring Ports in Verilog

Declaring ports in Verilog can be a tricky issue for beginners. Here is a brief of how and what to declare a port in Verilog HDL.

We will start dividing the ports on the basis of their location, i.e. input/output and on the basis of their behavior, i.e. registered data or simple wires.

On the basis of Location:-
We can group the ports into three on the basis of their locations :-
1) Input ports,
2) Output ports, and
3) Inout ports.

The input ports are basically the pins from where the data and signals reach the block. The output ports are the pins from where the data and signals leave the block. And the inouts are ports which can act as input and output during the run time.

On the basis of Behavior:-
We can group the ports into two on the basis of their behavior:-
1) Reg
2) Wire

If you want the data to be registered, then declare the port as reg. This will store the data/signal, which can be used later in the design. On the other hand, if you just want a signal to propagate from one point to another without any delay or storage, then declare it as the wire.

Even the inputs/outputs/inouts need to be declared on the basis of their behavior. Inputs are always wires, inouts are also always wire but outputs can be declared as wires or regs based on their behavior.

Refer to following diagram :-

Diagram Reference :- www.asic-world.com