Using Perl to instantiate Verilog modules

The detailed procedure to use perl to instantiate verilog modules has been given in the following link:-

Use Perl to Instatiate Verilog Modules By Jeremy Webb

This post is about the few problems I faced following the exact steps as per the link and the way I resolve those issues.

After downloading the package containing the .pm file and the perl script, i.e. .pl file, I tried to run make. I have not installed GCC feature in my cygwin as per now. So, there was no way I was getting the make command to run. So this is what I did.

I copied the .pm file to one of the locations already pointed by the path. To know the path, simply run the .pl file. The file will look for the .pm file in the locations defined by the path and when not found, it will send you the error report. In the error report look for the path that is assigned against @INC.

After copying the .pm file, simply execute the .pl file
The syntax would be:-
svtools.pl -i -f < Verilog_Filename >

Reference:-
Jeremy Webb's blog