Declare wires while using generate statements in Verilog

Even though there are intelligent guidelines for Verilog code writing, people rarely follow it. One of the cases is of declaring ports (wire and reg) in the verilog code.

Two common mistakes made while declaring ports are :-
1) Not declaring wire of single bit width.
2) Declaring wire in the middle or end of the code.

Guidelines will tell you to always declare ports and that too in the initial part of the code. Making the above mistakes may cause great problems, especially when the code contains generate blocks.

When generate blocks are used, the wires which are not declared above the generate block are generated for the instantiated blocks. The important fact here is that, these wires which are locally generated are inaccessible to the other upper level modules. Even if you declare wires after the generate block ends, it will perform the same above mentioned task. So, if you are making use of these wires to design the output, you will have serious problems in the operation of the code. The wires will be always low for the upper level modules.

An example is given below.


Here, dataOutTemp of the Test module will be always low. This will make dataOut of Test module tied to zero. To avoid such problems, always declare ports before the actual design code.

In the above case, to rectify the problem, we should declare the dataOutTemp as wire in line 11.