Declaring 2D Array I/O Ports in Verilog

2D arrays in verilog can be declared as :-
wire/reg [column_limit : 0] [0 : row_limit] ;

Eg:-
wire [7:0] byteMem [0:31]; => this creates a wire array of 8 bits * 32.

Using 2D arrays in verilog is a very tricky thing. System verilog supports 2D arrays but verilog seems to treat it as an estranged friend. Flexibility in assigning and accessing the 2D arrays are very hard. But as always, there are work arounds.

Verilog doesn't support 2D arrays as I/O ports. But there are cases when using and accessing 2D arrays are more efficient in reducing the code lines as well as improves the readability of the code. The work around for this is to declare the I/O ports as 1D array and use 2D wire internally which is then assigned the value as in the I/Os.

Suppose you need an output of 8bytes * 4 locations.
1) Assign the output as array of (8*4) width, i.e. [8*4-1:0]
2) Use an internal wire/reg array of 8bytes * 4 locations :-
wire [7:0] temp [0:3];
3) Using generate statement, assign the temp 2D array to store the values of the output array.
*Note :- A simple define could be used to assign the values. Refer to Comment #7 on the link below for more. Comment #7.

Simply use the macros defined in the link to implement virtual 2D array output/input ports.