Verilog :- Why not to use Blocking Statements in Sequential Logic Design

Although there is no golden rule in verilog as to which type of statements to use while designing sequential circuits, it is highly recommended that non-blocking statement be used while designing such circuits.

It is a very good and almost an essential practice to use blocking statements to design combinational block and non-blocking statements to design sequential logic.

When you have multi-cycle paths to be designed as a sequential logic, then the use of blocking statements usually leads to optimisation/trimming of the logic. For a 2 cycle delay, you will only get a single cycle of delay. Consider the following example :-

Case 1:- Sequential logic design with non-blocking statements:

Code:-

Rtl Schematic :-

Case 2:- Sequential logic design with Blocking statements:

Code:-

Rtl Schematic :-

So, non-blocking statements should be used while designing Sequential blocks in Verilog.

*Note :- The synthesis of code and rtl schematic generation were done using Xilinx ISE Release Version : 9.2.04i