Friday, July 22, 2011

Do not use % in the verilog code during Verilog Synthesis

When you need to find the remainder of a division operation, then %, i.e. Mod, is used. Suppose you want to find the remainder when 4 is divided by 3 then the code to implement is :-

When you are designing complex logics, use of Mod or % makes your work easier and also the code is more readable. The simulation of code with use of % works fine. But, when you move to synthesis, the code takes up so much time to synthesize. And honestly, I don't know if it will ever synthesize. I had a piece of code with % used at multiple places. After waiting for 40 odd minutes, the synthesis just stuck at 80%. It was trying to synthesize but I couldn't wait longer. After removing the % from the code, I got the whole code synthesized in less than 10 minutes. :)

So my advice to all the verilog coders will be to Feel free to use % if the code is meant for simulation. But Avoid usage of % in code that is to be synthesized. Rather use if..else statement, however lengthy they may be.

No comments :

Post a Comment